Generally, non-volatile semiconductor memory devices may include page buffers. The page buffers may latch data input/output to/from selected memory cells. The page buffers may be electrically connected to corresponding memory cells through conductive lines/connection nodes and bit lines.
FIG. 1 is a schematic diagram illustrating the layout of a conventional non-volatile semiconductor memory device. As shown in FIG. 1, page buffers PB1 to PB8 are arranged in groups of four. FIG. 1 shows that respective page buffers PB1 to PB4 and PB5 to PB8 include shielding devices TC1 to TC4 and TC5 to TC8. The shielding devices TC1 to TC4 and TC5 to TC8 may be selectively activated to respectively control the connections between the sensing terminals/sense amplifiers NSEN1 to NSEN4 and NSEN5 to NSEN8 and the connection nodes NCN1 to NCN4 and NCN5 to NCN8 of the page buffers PB1 to PB4 and PB5 to PB8. The connections between the connection nodes NCN1 to NCN4 and NCN5 to NCN8 and bit lines BLe1/BLo1 to BLe4/BLo4 and BLe5/BLo5 to BLe8/BLo8 (respectively corresponding to page buffers PB1 to PB4 and PB5 to PB8), are respectively controlled by isolation devices DTe1/DTo1 to DTe4/DTo4 and DTe5/DTo5 to DTe8/DTo8. For example, the bit line BLo4 of the page buffer PB4 is arranged to be adjacent to the connection node/connection line NCN5 of the page buffer PB5.
The capacitance of each bit line may be somewhat higher than the capacitance of each connection node. Therefore, during operation of the non-volatile semiconductor memory device (in particular, during an erase operation in which the voltage of the bit line may increase to a voltage level of about 20V), the voltage of a connection node adjacent to the bit line may also increase, due to capacitive coupling between the two. However, if the voltage of a connection node so coupled with a bit line increases to a relatively high voltage, a shielding device connected to the connection node (which may have a relatively low breakdown voltage) may be damaged. Therefore, in the layout of a non-volatile semiconductor memory device, preventing the voltage of a connection node adjacent to a bit line from increasing to such a high voltage level may be an important consideration.
However, as shown in the layout of FIG. 1, the connection node NCN5 has a relatively short length because it is connected to page buffer PB5, which is located in an uppermost position. Accordingly, the capacitance of the connection node NCN5 may be relatively low in comparison to the capacitance of the adjacent bit line Blo4. Therefore, when an erase voltage is applied to the bit line BLo4 during an erase operation, the voltage of the connection node NCN5 may be increased to a relatively high voltage due to the capacitive coupling between the two. As a result, the shielding device TC5 connected to the conductive line NCN5 may be damaged and/or destroyed.